This invention relates to a memory access control device for use in combination with request sources, a main memory, and an expanded memory to process a plurality of input requests supplied from the request sources.
A memory access control device of the type described is connected to request sources, to a main memory, and to an expanded memory. Each of the request sources is, for example, a central processing unit or a channel processing unit. The expanded memory may be a paging memory. The memory access control device successively processes a plurality of input requests supplied from the request sources. Each of the input requests is one of an access request indicative of access to the main memory, a first data transfer request indicative of transfer of data from the main memory to the expanded memory, and a second data transfer request indicative of transfer of data from the expanded memory to the main memory. The input request may be a diagnostic request indicative of detection of failure in the main memory.
A conventional memory access control device comprises a request receiving port section, a first preassigned access port section for access to the expanded memory, and a second preassigned access port section for access to the main memory. The request receiving port section is for receiving the input requests. The first preassigned access port section is for use in a first data transfer from the main memory to the expanded memory. The second preassigned access port section is for use in a second data transfer from the expanded memory to the main memory. In the conventional memory access control device, the request receiving port section judges whether each input request is identical with any one of the access requests, the first data transfer request, and the second data transfer request. Subsequently, the conventional memory access control device carries out processing by means of a result of that judgment as follows according to each of three cases:
(1) A first case where the input request in question is the access request. The request receiving port section carries out a first busy check for the main memory and processes the access request to supply the access request to the main memory. PA1 (2) A second case where the input request in question is the first data transfer request. PA1 (3) A third case where the input request in question is the second data transfer request.
The request receiving port section carries out the first busy check for the main memory and then supplies a first read request to the main memory. The first data transfer request is divided into a plurality of partial requests by the request receiving port section. When first transfer reply data is read out of the main memory in correspondence with all of the partial requests, the first data transfer request is delivered together with the first transfer reply data to the first preassigned access port section. The first preassigned access port section carries out a second busy check for the expanded memory and then supplies a first write-in request and the first transfer reply data to the expanded memory. Accordingly, the first data transfer is carried out.
The request receiving port section carries out a second busy check for the expanded memory and then supplies a second read request to the expanded memory. The second data transfer request is divided into a plurality of partial requests by the request receiving port section. When second transfer reply data is read out of the main memory in correspondence with all of the partial requests, the second data transfer request is delivered together with the second transfer reply data to the second preassigned access port section. The second preassigned access port section carries out the first busy check for the main memory and then supplies a second write-in request and the second transfer reply data to the main memory. Accordingly, the second data transfer is carried out.
As mentioned before, the conventional memory access control device first judges the type of each input request by the request receiving port section and then individually carries out the first and the second busy checks. As a result, the conventional memory access control device must carry out complex control functions.